Semiconductor devices, in particular power semiconductor devices, require an efficient edge termination to avoid electric field crowding at the edge of a main pn-junction resulting in breakdown of the device at a relatively low breakdown voltage VBR. Common power semiconductor devices, such as a pin diode or an insulated-gate bipolar transistor (IGBT), require an edge termination in order to achieve a breakdown voltage in the range of 80 to 90% of an ideal one-dimensional diode breakdown voltage.
For silicon-based devices, known planar edge termination techniques include junction termination extension (JTE), variation of lateral doping (VLD) and floating field ring (FFR) terminations with and without field plate extensions. Etched and refilled trenches have also been used. Silicon carbide (SiC) and especially 4H-SiC is an attractive material for high power semiconductor devices due to its 10 times higher critical electrical field than that of silicon. Given the well-known restrictions with SiC process technology, there are significant technological constraints. For example, when planar junctions are formed in SiC by implantation of impurities, the junction depth is limited to about 2 μm. The advantage of a FFR termination is due to the fact that the generation of the floating field rings can be easily integrated in the manufacturing process flow. It is possible to form the power semiconductor device with a FFR termination without increasing the mask count compared to a manufacturing process for the same power semiconductor device without the FFR termination. FFR terminations are often the first choice, in particular when manufacturing costs are of highest importance.
At present FFR terminations are mainly in use for low and medium voltage components (600 V to 3.3 kV IGBT, for example). For these voltage classes, appropriate breakdown voltages are achieved with ring systems comprising 3 to 10 rings. The design of a FFR termination for high voltage components is critical with regard to the wafer area occupied by the FFR termination, with regard to the breakdown voltage and with regard to the safe operating area (SOA) of the power semiconductor device including the FFR termination. The before-mentioned wafer area occupied by the FFR termination, the breakdown voltage and the safe operating area of the power semiconductor device including the FFR termination depend on a ring-to-ring separation and on the distance of the first innermost ring from the adjacent main pn-junction besides depending on the design parameters of each ring (such as the width of each ring and the doping profile of each ring).
Complex analytical methods have been developed to design an efficient FFR termination. From “An Improved Methodology for the CAD Optimization of Multiple Floating Field-Limiting Ring Terminations”, M. E. Baradai, IEEE Transactions on Electron Devices, vol. 58, No. 1, January 2011, pp. 266-270, there is known an analytical method for calculating ring-to-ring separations minimizing the area required for achieving a certain breakdown voltage. This analytical method for designing a FFR termination structure is complex in that it requires a high computational effort especially for a high total number of floating field rings. For a desired breakdown voltage an optimized FFR termination design with regard to the wafer area occupied by the FFR termination can be achieved with the method disclosed in this document. However, with regard to the safe operating area of the power semiconductor device, with this method optimum results cannot be achieved.
A less complicated design of a FFR termination is known from U.S. Pat. No. 5,075,739 A, in which a FFR termination is disclosed, wherein the ring-to-ring separation increases linearly in a lateral direction away from the main pn-junction. However, such design does also not result in optimum results with regard to the safe operating area of a power semiconductor device.
From the publication “Radiation-tolerant breakdown protection of silicon detectors using multiple floating guard rings” by Beck et al., Nucl. Instr. & Meth. in Phys. Res., Section A, vol. 396, no. 1-2, 1997, pages 214-227, there is known a multiple floating guard ring design which is optimized for high-voltage operation of silicon detectors. The distance between neighboring rings is constant in a first zone adjacent to a central diode and is increasing from inside to outside with a constant rate in a second zone.